/* mot83xxPci.h - Motorola ads 83xx PCI Bridge setup header file */

/* Copyright 1984-2005 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------

01a,04jul02,dtr  File created form mot85xxPci.h
*/

#ifndef _INCmot83xxPcih
#define _INCmot83xxPcih

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */



#define COMMAND_REGISTER_OFFSET         0x4
#define COMMAND_REGISTER_WIDTH          0x2        
#define BRIDGE_BAR0_OFFSET              0x10
#define BRIDGE_BAR0_WIDTH               0x4



/* Outbound translation registers FIx offsets??? TBD */
#define PCI_OUTBOUND_TRANS_ADRS_REGn(base,n)     \
    (CAST(VUINT32 *)((base) + 0x8400 + n*0x18))

#define PCI_OUTBOUND_TRANS_EXT_ADRS_REGn(base,n)     \
      (CAST(VUINT32 *)((base) + 0x8404 + (n*0x18)))

#define PCI_OUTBOUND_BASE_ADRS_REGn(base,n)     \
      (CAST(VUINT32 *)((base) + 0x8408 + n*0x18))

/* Outbound attributes register definitions */ 
#define PCI_OUTBOUND_ATTR_REGn(base,n)     (CAST(VUINT32 *)((base) + 0x8410 + (n*0x18)))

/* Outbound/Inbound Comparison mask register defines */
#define PCI_WINDOW_ENABLE_BIT 0x80000000
#define PCI_ATTR_BS_BIT       0x40000000
#define PCI_OUT_ATTR_RTT_MEM      0x00040000
#define PCI_OUT_ATTR_RTT_IO       0x00080000
#define PCI_OUT_ATTR_WTT_MEM      0x00004000
#define PCI_OUT_ATTR_WTT_IO       0x00008000 
#define PCI_ATTR_WS_4K       0x0000000B
#define PCI_ATTR_WS_8K       0x0000000c
#define PCI_ATTR_WS_16K      0x0000000D
#define PCI_ATTR_WS_32K      0x0000000E
#define PCI_ATTR_WS_64K      0x0000000F
#define PCI_ATTR_WS_128K     0x00000010
#define PCI_ATTR_WS_256K     0x00000011
#define PCI_ATTR_WS_512K     0x00000012
#define PCI_ATTR_WS_1M       0x00000013
#define PCI_ATTR_WS_2M       0x00000014
#define PCI_ATTR_WS_4M       0x00000015
#define PCI_ATTR_WS_8M       0x00000016
#define PCI_ATTR_WS_16M      0x00000017
#define PCI_ATTR_WS_32M      0x00000018
#define PCI_ATTR_WS_64M      0x00000019
#define PCI_ATTR_WS_128M     0x0000001a
#define PCI_ATTR_WS_256M     0x0000001b
#define PCI_ATTR_WS_512M     0x0000001c
#define PCI_ATTR_WS_1G       0x0000001d
#define PCI_ATTR_WS_2G       0x0000001e
#define PCI_ATTR_WS_4G       0x0000001f
#define PCI_IN_ATTR_TGI_LM   0x00f00000
#define PCI_IN_ATTR_TGI_RIO  0x00c00000
#define PCI_IN_ATTR_RTT_RIO_READ 0x00040000
#define PCI_IN_ATTR_RTT_LM_READ_NO_SNOOP 0x00040000
#define PCI_IN_ATTR_RTT_LM_READ_SNOOP 0x00050000
#define PCI_IN_ATTR_RTT_LM_READ_UNLOCK_L2_CACHE_LINE 0x00070000
#define PCI_IN_ATTR_RTT_LM_WRITE_NO_SNOOP 0x00004000
#define PCI_IN_ATTR_RTT_LM_WRITE_SNOOP 0x00005000
#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_L2_CACHE_LINE 0x00006000
#define PCI_IN_ATTR_RTT_LM_WRITE_ALLOC_LOCK_L2_CACHE_LINE 0x00007000

#define PCI_SNOOP_ENABLE        0x40000000
#define PCI_PREFETCHABLE        0x20000000


#define PCI1_GCR(base) (CAST(VUINT32 *)((base) + 0x8520))
#define PCI1_ECR(base) (CAST(VUINT32 *)((base) + 0x8524))
#define PCI1_GSR(base) (CAST(VUINT32 *)((base) + 0x8528))

#define PCI2_GCR(base) (CAST(VUINT32 *)((base) + 0x8620))
#define PCI2_ECR(base) (CAST(VUINT32 *)((base) + 0x8624))
#define PCI2_GSR(base) (CAST(VUINT32 *)((base) + 0x8628))

/* Inbound translation registers FIx Offsets ???? */
#define PCI1_INBOUND_TRANS_ADRS_REGn(base,n)     \
      (CAST(VUINT32 *)((base) + 0x8568 - (n * 0x18)))
#define PCI1_INBOUND_EXT_BASE_ADRS_REGn(base,n) \
      (CAST(VUINT32 *)((base) + 0x8574 - (n * 0x18)))
#define PCI1_INBOUND_BASE_ADRS_REGn(base,n)      \
      (CAST(VUINT32 *)((base) + 0x8570 - (n * 0x18)))
#define PCI1_INBOUND_ATTR_REGn(base,n)          \
      (CAST(VUINT32 *)((base) + 0x8578 - (n * 0x18)))

/* Inbound translation registers FIx Offsets ???? */
#define PCI2_INBOUND_TRANS_ADRS_REGn(base,n)     \
      (CAST(VUINT32 *)((base) + 0x8668 - (n*0x18)))
#define PCI2_INBOUND_EXT_BASE_ADRS_REGn(base,n) \
      (CAST(VUINT32 *)((base) + 0x8674 - (n * 0x18)))
#define PCI2_INBOUND_BASE_ADRS_REGn(base,n)      \
      (CAST(VUINT32 *)((base) + 0x8670))
#define PCI2_INBOUND_ATTR_REGn(base,n)          \
      (CAST(VUINT32 *)((base) + 0x8678 - (n * 0x18)))

/* PCI error Registers */
#define PCI1_ESR(base) (CAST(VUINT32 *)((base) + 0x8500))
#define PCI1_ERROR_ERROR_STATUS_REG       0x8500
#define PCI1_ERROR_CAPTURE_DISABLE_REG    0x8504
#define PCI1_ERROR_ENABLE_REG             0x8508
#define PCI1_ERROR_ATTR_CAPTURE_REG       0x850c
#define PCI1_ERROR_ADRS_CAPTURE_REG       0x8510
#define PCI1_ERROR_EXT_ADRS_CAPTURE_REG   0x8514
#define PCI1_ERROR_DATA_LOW_CAPTURE_REG   0x8518
#define PCI1_ERROR_DATA_HIGH_CAPTURE_REG  0x851c
#define PCI1_ERROR_GASKET_TIMER_REG       0x8520

/* PCI error Registers */
#define PCI2_ESR(base) (CAST(VUINT32 *)((base) + 0x8600))
#define PCI2_ERROR_ERROR_STATUS_REG       0x8600
#define PCI2_ERROR_CAPTURE_DISABLE_REG    0x8604
#define PCI2_ERROR_ENABLE_REG             0x8608
#define PCI2_ERROR_ATTR_CAPTURE_REG       0x860c
#define PCI2_ERROR_ADRS_CAPTURE_REG       0x8610
#define PCI2_ERROR_EXT_ADRS_CAPTURE_REG   0x8614
#define PCI2_ERROR_DATA_LOW_CAPTURE_REG   0x8618
#define PCI2_ERROR_DATA_HIGH_CAPTURE_REG  0x861c
#define PCI2_ERROR_GASKET_TIMER_REG       0x8520

/* Comand status register defines */
#define BUS_MASTER_ENABLE_BIT   0x4
#define MEMORY_SPACE_ACCESS_ENABLE_BIT 0x2

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#endif /* _INCmot83xxPcih */

